1. Field of the Invention
This invention relates generally to analog to digital converters and, more particularly, to apparatus for correcting an input offset voltage by applying a correction signal to the input signal.
2. Description of the Related Art
It is well known in a Pulse Code Modulation circuit to provide an analog-to-digital converter to provide a digital output signal determined by an input analog signal. An input signal is typically applied to a filter prior to application to the analog-to-digital converter. The presence of the filter can result in an offset voltage signal as part input signal applied to the analog-to-digital converter.
Referring now to FIG. 1, an analog to digital converter transfer characteristic (according to a circuit implementation referred to as an A-Law encoder) is shown. The larger segments of FIG. 1 are generally called chords and the incremental steps within each chord are referred to as steps. There are 16 chords (8 positive chords and 8 negative chords) with 16 segments per chord, making a total of 256 break points that can be encoded with an 8 bits output signal of an analog-to-digital encoder. The most significant bit of the digital output signal group (word) is the sign, the next three most significant bits indicate which of the 8 chords is being referred to (the larger the chord value, the larger the value of the voltage), and the last four of the 8 bits represent the step within the chord. Pulse Code Modulation analog-to-digital converters are generally divided into two portions, each of the portions identified with encoding of the a portion of the graph described above. An upper array of capacitors implements the encoding of the chords, while a lower array of capacitors implements the encoding of the steps within the chords.
Referring now to FIG. 2, a simplified schematic diagram of the two portions of the analog-to-digital converter is shown. The analog to digital conversion process as implemented by the converter shown in FIG. 2 is accomplished in the following manner. With the switch S1 turned on, the group of switches S2 are in position a so that the (analog) input signal is stored on the capacitor array. Next, the switch S1 is turned to the off position, i.e. removes the capacitor bank from ground, and the group of switches S2 turns to the b position so that the input of the comparator or summing node has a voltage equal to the input signal, but of opposite polarity. This first comparison gives the sign of the input signal which in turn gives the sign of the reference voltage that is to be used, i.e. +V.sub.ref -V.sub.ref. This initial operation determines the sign bit. After the sign of the output signal group has been determined, the appropriate reference voltage determined in the prior step, is applied to at least one capacitor terminal. The charge on the capacitor terminal is then distributed among the other capacitors to provide a voltage input to the comparator circuit and depending on the results of the comparator, a next approximation is attempted. Referring to FIG. 3, a decision tree is shown indicating how the successive approximation register technique is implemented. At each point at the decision tree, a determination is made if the resulting voltage from the input charge distributed among the capacitors is greater or is less than the input voltage. The next operation either increases or decreased the input charge and therefore the signal according to the result of the preceding comparison. Table 1 is included to show more details of the successive approximation technique as is implemented in the apparatus of FIG. 2.
TABLE 1 ______________________________________ (A-LAW) POSITIONS OF THE SWITCHES SAR WEIGHT c d b ______________________________________ 000 0 / S20 S21-S27 001 64 S20 S21 S22-S27 010 128 S20-S21 S22 S23-S27 011 256 S20-S22 S23 S24-S27 100 512 S20-S23 S24 S25-S27 101 1024 S20-S24 S25 S26-S27 110 2048 S20-S25 S26 S27 111 4096 S20-S26 S27 / ______________________________________ Reference Weight = 8192 c = .+-.VREF D = Output of the lower OP. AMP. b = GND
The encoding operation is continued until the correct chord (referred to FIG. 1) has been identified. Once the chord has been determined, then the similar procedure is performed on the lower array for the step of the chord. The encoding process is performed for the lower array in a manner similar to the upper array. However, unlike the switches in the upper array, there is a direct correspondence between the four lower bits of the successive approximation register and the switches S3. For example, if the bit is a logic 1, switch S3 is in position b, otherwise switch S3 is in position a. It should be noted that for the particular configuration of the analog-to-digital converter shown in FIG. 2, the V.sub.ref used in the lower array has the opposite sign of the V.sub.ref used in the upper array.
Because of the different sources of errors present in the circuit, such as offset voltages in the comparator and in the previous stages of the system, the desired value of the voltage stored at summing node is not equal to -V.sub.in but equal to -V.sub.in plus V.sub.offset. In the implementation in which the value of the V.sub.off is digitally stored in a dedicated offset voltage correction register, this correction is obtained by performing a digital-to-analog conversion of the dedicated register contents and application of the results to the input terminal of the analog to digital conversion.
A need has therefore been felt for apparatus and method for implementing the correction of the voltage at the summing node of the analog-to-digital converter for offset voltages and other error voltage levels without affecting the performance of the converter.